1. Field of the Invention
The present invention relates to a technique for reducing power supply current surges in dynamic transmission gate logic circuits.
2. Description of the Prior Art
Logic integrated circuits, including complementary metal oxide silicon (CMOS) types, are generally classified as being "static" or "dynamic". The static types usually allow for a logic signal to be applied at any time, and immediately generate the resulting logic output signal. The dynamic types generally employ one or more clocked transistors that provide for generating the logical output in synchronism with the clock. One known type of dynamic logic is "transmission gate logic". Referring to FIG. 4, a typical dynamic register cell comprising two stages is shown. In the first stage, a pair of complementary pass transistors (40, 41) allows a logic signal to propagate from the input node (INPUT DATA) to storage node I1, in response to a "master" clock signal and its complement (MCK, MCKB) that is applied to the transistor gates. The logic signal thus appears at the input of an inverter comprising a serially connected complementary transistor pair (42,43). A second stage comprises pass transistors (44,45) controlled by a "slave" clock and its complement (SCK, SCKB). These pass transistors allow the signal to propagate from the output node of the first inverter (I2) to storage node I3, and hence to inverter (46,47) and the output node (OUTPUT). When the pass transistors 40, 41 are non-conducting, the storage node I1 floats in potential. Similarly, when pass transistors 44, 45 are non-conducting, storage node I3 floats. In one variation of this technique, a single pass transistor (e.g., 40, 44) may be used per stage, with a reduction in the clock signals required (e.g., MCK, SCK).
A plurality of transmission gate cells may be combined by connecting their output nodes to an inverter, allowing for complex logic operations using a plurality of logic input signals. In one current design, over 7000 cells on a single integrated circuit are utilized in this fashion. In another arrangement, the cells are utilized to implement a shift register that delays an input signal a desired amount. One important criterion for logic circuits, especially dynamic types, is their power consumption. It is important that the desired implementation not draw excessive current. In particular, as the number of cells per integrated circuit increase, the tendency is for the power consumption to increase. One problem encountered in field effect technology (e.g., CMOS) is that "floating input nodes" may exist when the clock signal disappears. In that case, the inputs to the inverters may float to a potential that allows DC current flow through the inverters. One solution is to provide a negative feedback circuit that clamps the input to a known state (either high or low); see U.S. Pat. No. 4,570,219. That effectively converts the device from a dynamic to a static type. However, that requires additional circuitry in each stage being protected, which increases the cell size of transmission gate logic circuits.